Four-quadrant one-transistor-synapse for high-density CNN implementations

Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and result...

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Bibliographic Details
Main Authors: Dominguez-Castro, R., Rodriguez-Vazquez, A., Espejo, S., Carmona, R.
Format: Conference Proceeding
Language:English
Subjects:
Analog processing circuits
Artificial neural networks
Cellular neural networks
CMOS process
CMOS technology
Energy consumption
Power dissipation
Proposals
Signal processing
Voltage
Online Access:Request full text
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Description
Summary:Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.
DOI:10.1109/CNNA.1998.685377