Loading…
Four-quadrant one-transistor-synapse for high-density CNN implementations
Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and result...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Conference Proceeding |
| Language: | English |
| Subjects: | |
| Online Access: | Request full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| cited_by | |
|---|---|
| cites | |
| container_end_page | 248 |
| container_issue | |
| container_start_page | 243 |
| container_title | |
| container_volume | |
| creator | Dominguez-Castro, R. Rodriguez-Vazquez, A. Espejo, S. Carmona, R. |
| description | Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip. |
| doi_str_mv | 10.1109/CNNA.1998.685377 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_685377</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>685377</ieee_id><sourcerecordid>685377</sourcerecordid><originalsourceid>FETCH-LOGICAL-i146t-59d2aa76a4dad832ad24c1a76f2ef40502e67b3489182e651dbdccaf953606323</originalsourceid><addsrcrecordid>eNotT0tLAzEYDIhQrb0XT_sHsub9OJbFaqHUi57L103WRroPk_Sw_95AncsMMzDfNwitKakpJfalORw2NbXW1MpIrvUdeiTaEC6M0myBVin9kAIhJeXqAe224zXi3yu4CEOuxsHjXFQKKY8Rp3mAKfmqG2N1Dt9n7HyJ8lyVK1Xop4vv_ZAhh3FIT-i-g0vyq39eoq_t62fzjvcfb7tms8eBCpWxtI4BaAXCgTOcgWOipcXomO8EkYR5pU_lXUtNkZK6k2tb6KzkiijO-BI933qD9_44xdBDnI-3sfwP_1RLSg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Four-quadrant one-transistor-synapse for high-density CNN implementations</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Dominguez-Castro, R. ; Rodriguez-Vazquez, A. ; Espejo, S. ; Carmona, R.</creator><creatorcontrib>Dominguez-Castro, R. ; Rodriguez-Vazquez, A. ; Espejo, S. ; Carmona, R.</creatorcontrib><description>Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.</description><identifier>ISBN: 0780348672</identifier><identifier>ISBN: 9780780348677</identifier><identifier>DOI: 10.1109/CNNA.1998.685377</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analog processing circuits ; Artificial neural networks ; Cellular neural networks ; CMOS process ; CMOS technology ; Energy consumption ; Power dissipation ; Proposals ; Signal processing ; Voltage</subject><ispartof>1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359), 1998, p.243-248</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/685377$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/685377$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Dominguez-Castro, R.</creatorcontrib><creatorcontrib>Rodriguez-Vazquez, A.</creatorcontrib><creatorcontrib>Espejo, S.</creatorcontrib><creatorcontrib>Carmona, R.</creatorcontrib><title>Four-quadrant one-transistor-synapse for high-density CNN implementations</title><title>1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)</title><addtitle>CNNA</addtitle><description>Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.</description><subject>Analog processing circuits</subject><subject>Artificial neural networks</subject><subject>Cellular neural networks</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Energy consumption</subject><subject>Power dissipation</subject><subject>Proposals</subject><subject>Signal processing</subject><subject>Voltage</subject><isbn>0780348672</isbn><isbn>9780780348677</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotT0tLAzEYDIhQrb0XT_sHsub9OJbFaqHUi57L103WRroPk_Sw_95AncsMMzDfNwitKakpJfalORw2NbXW1MpIrvUdeiTaEC6M0myBVin9kAIhJeXqAe224zXi3yu4CEOuxsHjXFQKKY8Rp3mAKfmqG2N1Dt9n7HyJ8lyVK1Xop4vv_ZAhh3FIT-i-g0vyq39eoq_t62fzjvcfb7tms8eBCpWxtI4BaAXCgTOcgWOipcXomO8EkYR5pU_lXUtNkZK6k2tb6KzkiijO-BI933qD9_44xdBDnI-3sfwP_1RLSg</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Dominguez-Castro, R.</creator><creator>Rodriguez-Vazquez, A.</creator><creator>Espejo, S.</creator><creator>Carmona, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1998</creationdate><title>Four-quadrant one-transistor-synapse for high-density CNN implementations</title><author>Dominguez-Castro, R. ; Rodriguez-Vazquez, A. ; Espejo, S. ; Carmona, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i146t-59d2aa76a4dad832ad24c1a76f2ef40502e67b3489182e651dbdccaf953606323</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Analog processing circuits</topic><topic>Artificial neural networks</topic><topic>Cellular neural networks</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Energy consumption</topic><topic>Power dissipation</topic><topic>Proposals</topic><topic>Signal processing</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Dominguez-Castro, R.</creatorcontrib><creatorcontrib>Rodriguez-Vazquez, A.</creatorcontrib><creatorcontrib>Espejo, S.</creatorcontrib><creatorcontrib>Carmona, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dominguez-Castro, R.</au><au>Rodriguez-Vazquez, A.</au><au>Espejo, S.</au><au>Carmona, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Four-quadrant one-transistor-synapse for high-density CNN implementations</atitle><btitle>1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)</btitle><stitle>CNNA</stitle><date>1998</date><risdate>1998</risdate><spage>243</spage><epage>248</epage><pages>243-248</pages><isbn>0780348672</isbn><isbn>9780780348677</isbn><abstract>Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.</abstract><pub>IEEE</pub><doi>10.1109/CNNA.1998.685377</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 0780348672 |
| ispartof | 1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359), 1998, p.243-248 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_685377 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog processing circuits Artificial neural networks Cellular neural networks CMOS process CMOS technology Energy consumption Power dissipation Proposals Signal processing Voltage |
| title | Four-quadrant one-transistor-synapse for high-density CNN implementations |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T19%3A50%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Four-quadrant%20one-transistor-synapse%20for%20high-density%20CNN%20implementations&rft.btitle=1998%20Fifth%20IEEE%20International%20Workshop%20on%20Cellular%20Neural%20Networks%20and%20their%20Applications.%20Proceedings%20(Cat.%20No.98TH8359)&rft.au=Dominguez-Castro,%20R.&rft.date=1998&rft.spage=243&rft.epage=248&rft.pages=243-248&rft.isbn=0780348672&rft.isbn_list=9780780348677&rft_id=info:doi/10.1109/CNNA.1998.685377&rft_dat=%3Cieee_6IE%3E685377%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i146t-59d2aa76a4dad832ad24c1a76f2ef40502e67b3489182e651dbdccaf953606323%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=685377&rfr_iscdi=true |