Hardware implementation of a wavelet based image compression coder

A VLSI architecture designed to perform real-time image compression using wavelets is described. The two basic modules of the architecture are a 2-D wavelet transform generator and a coder based on the SPIHT algorithm for lossy image compression. A folded architecture is proposed for computing the 2...

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Bibliographic Details
Main Authors: Singh, J., Antoniou, A., Shpak, D.J.
Format: Conference Proceeding
Language:English
Subjects:
Associative memory
Computer architecture
Concurrent computing
Filters
Graphics
Hardware
Image coding
Random access memory
Very large scale integration
Wavelet transforms
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Description
Summary:A VLSI architecture designed to perform real-time image compression using wavelets is described. The two basic modules of the architecture are a 2-D wavelet transform generator and a coder based on the SPIHT algorithm for lossy image compression. A folded architecture is proposed for computing the 2-D wavelet transform. The architecture uses 3 parallel computational units and 2 storage units. The hardware for the SPIHT coder uses 2 content addressable memories and 3 random access memories. The designs are modular and can easily be extended for different levels of wavelet decomposition and filter lengths. The derived architecture has been functionally verified for an 8/spl times/8 image size by simulating its VHDL code using Mentor Graphics.
DOI:10.1109/ADFSP.1998.685718