Design of Efficient Content Addressable Memories in High-Performance FinFET Technology

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2015-05, Vol.23 (5), p.963-967
• Main Authors: Bhattacharya, Debajit, Bhoj, Ajay N., Jha, Niraj K.
• Format: Article
• Language: English
• Subjects: Cams; Capacitance; Computer aided manufacturing; Content addressable memories (CAMs); FinFET; FinFETs; Layout; Logic gates; Measurement; parasitic extraction; technology computer-aided design (TCAD)
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2319192

Content addressable memories (CAMs) enable high-speed parallel search operations in table lookup-based applications, such as Internet routers and processor caches. Traditional CAM design has always suffered from the high dynamic power consumption associated with its large and active parallel hardware. However, deeply scaled technology nodes, with multigate devices replacing planar MOSFETs, are expected to bring new tradeoffs to CAM design. FinFET, a vertical-channel gate-wrap-around double-gate device, has emerged as the best alternative to planar MOSFET. In this brief, for the first time, we explore the design space of symmetric and asymmetric gate-workfunction FinFET CAMs. We propose several design alternatives and evaluate them in terms of their dc and transient metrics for different mismatch probabilities using technology computer-aided design simulations with 22-nm FinFET devices. We also propose two orthogonal layout styles for CAM design and show that one of them (vertical-search line) outperforms the other (vertical-match line) in terms of total power (22.3%) and search delay (5.8%).