A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC

A continuous time 5-bit feed forward ΔΣ ADC architecture is presented, which measures 97.3 dB SNR, over 600 kHz bandwidth while consuming 31 mW/channel. This performance is achieved by using an ISI mitigation scheme and a 2 nd -order DEM for 3-level DACs along with analog low power techniques. The 0...

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Bibliographic Details
Main Authors: Bandyopadhyay, Abhishek, Adams, Robert, Khiem Nguyen, Baginski, Paul, Lamb, David, Tansley, Thomas
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Clocks
Signal to noise ratio
Split gate flash memory cells
Switches
Topology
Online Access:Request full text
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Description
Summary:A continuous time 5-bit feed forward ΔΣ ADC architecture is presented, which measures 97.3 dB SNR, over 600 kHz bandwidth while consuming 31 mW/channel. This performance is achieved by using an ISI mitigation scheme and a 2 nd -order DEM for 3-level DACs along with analog low power techniques. The 0.99mm 2 /channel chip was fabricated in 0.18um CMOS process, and achieves a FOM of 171.8 dB.
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2014.6858397