Backside device physical analysis for yield and reliability of advanced bulk-Si CMOS ICs

This paper presents an effective backside device physical analysis methodology for identification of defects and weaknesses from design or manufacturing in advanced flip-chip packaged bulk-Si CMOS ICs. Case studies demonstrate applications of the methodology and techniques in failure analysis and pr...

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Bibliographic Details
Main Authors: Yuanjing Li, Marks, Howard Lee
Format: Conference Proceeding
Language:English
Subjects:
Bulk silicon backside de-process
Dielectrics
e-fuse
EBAC
FIB
Fuses
Logic gates
OPC end-result
Scanning electron microscopy
SEM
Silicides
Silicon
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Description
Summary:This paper presents an effective backside device physical analysis methodology for identification of defects and weaknesses from design or manufacturing in advanced flip-chip packaged bulk-Si CMOS ICs. Case studies demonstrate applications of the methodology and techniques in failure analysis and process evaluation of 28nm CMOS devices and beyond for yield and reliability enhancement.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2014.6860636