System-level modeling of microprocessor reliability degradation due to BTI and HCI

Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI) and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of NBTI, PBTI and HCI on state-of-art microprocessors a...

Full description

Saved in:
Bibliographic Details
Main Authors: Chang-Chih Chen, Soonyoung Cha, Taizhi Liu, Milor, Linda
Format: Conference Proceeding
Language:English
Subjects:
aging
Benchmark testing
cache
Degradation
hot carrier injection
Human computer interaction
microprocessor
Microprocessors
modeling
negative bias temperature instability
positive bias temperature instability
reliability
SRAM
Stress
Threshold voltage
timing analysis
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI) and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of NBTI, PBTI and HCI on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we do timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to BTI and HCI. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to provide insights on reliability of memories embedded within microprocessors under realistic use conditions.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2014.6861125