dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects

Designing dependable on-chip manycore systems is subjected to consideration of multiple reliability threats, i.e. soft errors, aging, process variation, etc. In this paper, we introduce a novel adaptive Dependability Tuning (dTune) scheme for many-core processors. It leverages the knowledge of varyi...

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Bibliographic Details
Main Authors: Rehman, Semeen, Kriebel, Florian, Sun, Duo, Shafique, Muhammad, Henkel, Jörg
Format: Conference Proceeding
Language:English
Subjects:
Aging
Degradation
Delays
Hardware
Hardware > Hardware test
Hardware > Robustness
Program processors
Software reliability
Tuning
Online Access:Request full text
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Summary:Designing dependable on-chip manycore systems is subjected to consideration of multiple reliability threats, i.e. soft errors, aging, process variation, etc. In this paper, we introduce a novel adaptive Dependability Tuning (dTune) scheme for many-core processors. It leverages the knowledge of varying vulnerability and error masking properties of different applications along with multiple compiled versions (each offering distinct reliability and performance properties). Our dTune system dynamically tunes the dependability mode at the hardware level through hybrid Redundant Multithreading tuning and at the software level through selection of reliable code version under given performance constraints. It jointly accounts for soft errors and cores' performance variations due to design-time process variation and/or run-time aging-induced performance degradation. We compare our dTune system with four different state-of-the-art techniques and achieve on average 44% and up to 63% improved task reliability for different chip configurations, different variability maps, and different aging years.
ISSN:0738-100X
DOI:10.1145/2593069.2593127