Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits

The increasing cost paid in clocking integrated circuits and combating timing variations forces designers to rethink asynchronous approaches to system realization. Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption. Its expensive log...

Full description

Saved in:
Bibliographic Details
Main Authors: Chuang, Chi-Chuan, Lai, Yi-Hsiang, Jiang, Jie-Hong R.
Format: Conference Proceeding
Language:English
Subjects:
Asynchronous Pipeline
Delays
Half Buffer
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Integrated circuit modeling
Libraries
Logic gates
Performance analysis
Pipelines
Quasi-Delay Insensitivity
Static Performance Analysis
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The increasing cost paid in clocking integrated circuits and combating timing variations forces designers to rethink asynchronous approaches to system realization. Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption. Its expensive logic overhead, however, often nullifies its promise of performance and power improvements, and remains a major obstacle against its adoption. To overcome this obstacle, this paper proposes an efficient static performance analysis procedure and a synthesis flow for precharged half buffer (PCHB) and weak-conditioned half buffer (WCHB) circuit optimization. Experimental results demonstrate efficient performance analysis and effective area reduction under pipeline cycle time constraints.
ISSN:0738-100X
DOI:10.1145/2593069.2593224