A 40ns 64Mb DRAM With Current-sensing Data-bus Amplifier

This 64Mb DRAM with a current-sensing data bus amplifier combined with bus-line-on-cell chip architecture provides parallel wide-band data processing of 64b compressed test functions. Column-select lines are separated for read and write operations to enable immediate operation change. In ad­ dition,...

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Bibliographic Details
Main Authors: Taguchi, M., Tomita, H., Uchida, T., Oonishi, Y., Sato, K., Ema, T., Higashitani, M., Nakagawa, K., Kanazawa, M., Yabu, T.
Format: Conference Proceeding
Language:English
Subjects:
Broadband amplifiers
Circuit testing
Delay lines
Feedback circuits
Flip-flops
MOSFETs
Random access memory
Switches
Timing
Voltage
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Description
Summary:This 64Mb DRAM with a current-sensing data bus amplifier combined with bus-line-on-cell chip architecture provides parallel wide-band data processing of 64b compressed test functions. Column-select lines are separated for read and write operations to enable immediate operation change. In ad­ dition, sense amplifiers are isolated from data bus lines so that column selection can be independent of sense amplifier activa­ tion timing. 40ns typical RAS access time is obtained.
DOI:10.1109/ISSCC.1991.689086