33 nm ultra-shallow junction technology by oxygen-free and point-defect reduction process

This paper investigates the effect of I/I point-defect and the impact of surface-oxide during RTA, and proposes a novel junction formation process for realizing ultra-shallow junctions. In this technology, SD-extensions are fabricated using 0.5 keV ultra-low energy single-B I/I without gate-sidewall...

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Bibliographic Details
Main Authors: Shishiguchi, S., Mineji, A., Yasunaga, T., Saito, S.
Format: Conference Proceeding
Language:English
Subjects:
Boron
Degradation
Design for quality
Fabrication
Laboratories
National electric code
Space technology
Surface resistance
Temperature
Ultra large scale integration
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Summary:This paper investigates the effect of I/I point-defect and the impact of surface-oxide during RTA, and proposes a novel junction formation process for realizing ultra-shallow junctions. In this technology, SD-extensions are fabricated using 0.5 keV ultra-low energy single-B I/I without gate-sidewall spacers nor screen-oxide, followed by high temperature (1000/spl deg/C) RTA in pure-N/sub 2/ ambient without cover-oxide. These conditions realize shallow extensions (33 nm) with low sheet-resistance (660 /spl Omega//sq) and low off-current for PMOS-FETs. Ge pre-amorphization (5 keV) technology is applied to the deep-SD fabrication by 2 keV B implantation. This Ge pre-amorphization technique decreases the point-defects caused by the deep-SD implantation; resulting in the reduction of transient enhanced diffusion of SD-extension regions. These conditions for both the SD-extensions and deep-SDs are essential to achieve deep sub-quarter micron MOS-FETs by implantation technology.
DOI:10.1109/VLSIT.1998.689230