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Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

A scalable multi-V T enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-V T is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work fun...

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Main Authors: Ragnarsson, Lars-Ake, Chew, S. A., Dekkers, H., Luque, M. Toledano, Parvais, B., De Keersgieter, A., Devriendt, K., Van Ammel, A., Schram, T., Yoshida, N., Phatak, A., Han, K., Colombeau, B., Brand, A., Horiguchi, N., Thean, A. V.-Y
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creator Ragnarsson, Lars-Ake
Chew, S. A.
Dekkers, H.
Luque, M. Toledano
Parvais, B.
De Keersgieter, A.
Devriendt, K.
Van Ammel, A.
Schram, T.
Yoshida, N.
Phatak, A.
Han, K.
Colombeau, B.
Brand, A.
Horiguchi, N.
Thean, A. V.-Y
description A scalable multi-V T enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-V T is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack T inv , J G , D IT and reliability as well as the device performance are shown to be unaffected by the multi V T process.
doi_str_mv 10.1109/VLSIT.2014.6894359
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fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_6894359</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6894359</ieee_id><sourcerecordid>6894359</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-8b2ab63cf0d6b2afef0c71f50307d72a49497448a4046a1c6ac7030ab2f686433</originalsourceid><addsrcrecordid>eNo1UMFOwzAUCwIktrEfgMv7gY6XJk2aIxqMTSriQLXrlKbpFtal05oO9cC_U4lxsi3LtmRCHijOKEX1tM4-V_ksRspnIlWcJeqKjCmXSjHG4uSaTJVM_zXFGzJCyVlEExHfkXHbfiHGmLB0RH6Wbrure2iNrnVRWyi6eg8L5xevObzYszO2hW8XdvDe1cFF6xyaY3CNb6HowTS-7ExwZwsHG3QNWx0stEGbPYTOO7-FqjlB2FmgGPkD-Ka0oH0Jhe2H7D25rXTd2ukFJyQfdufLKPt4W82fs8gpDFFaxLoQzFRYioFWtkIjaZUgQ1nKWHPFleQ81Ry50NQIbeTg6SKuRCo4YxPy-FfrrLWb48kd9KnfXJ5jvzC5YJs</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond</title><source>IEEE Xplore All Conference Series</source><creator>Ragnarsson, Lars-Ake ; Chew, S. A. ; Dekkers, H. ; Luque, M. Toledano ; Parvais, B. ; De Keersgieter, A. ; Devriendt, K. ; Van Ammel, A. ; Schram, T. ; Yoshida, N. ; Phatak, A. ; Han, K. ; Colombeau, B. ; Brand, A. ; Horiguchi, N. ; Thean, A. V.-Y</creator><creatorcontrib>Ragnarsson, Lars-Ake ; Chew, S. A. ; Dekkers, H. ; Luque, M. Toledano ; Parvais, B. ; De Keersgieter, A. ; Devriendt, K. ; Van Ammel, A. ; Schram, T. ; Yoshida, N. ; Phatak, A. ; Han, K. ; Colombeau, B. ; Brand, A. ; Horiguchi, N. ; Thean, A. V.-Y</creatorcontrib><description>A scalable multi-V T enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-V T is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack T inv , J G , D IT and reliability as well as the device performance are shown to be unaffected by the multi V T process.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 9781479933310</identifier><identifier>ISBN: 1479933317</identifier><identifier>EISBN: 1479933325</identifier><identifier>EISBN: 1479933309</identifier><identifier>EISBN: 9781479933303</identifier><identifier>EISBN: 9781479933327</identifier><identifier>DOI: 10.1109/VLSIT.2014.6894359</identifier><language>eng</language><publisher>IEEE</publisher><subject>Doping ; FinFETs ; Implants ; Logic gates ; Nitrogen ; Tin</subject><ispartof>2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6894359$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27924,54554,54931</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6894359$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ragnarsson, Lars-Ake</creatorcontrib><creatorcontrib>Chew, S. A.</creatorcontrib><creatorcontrib>Dekkers, H.</creatorcontrib><creatorcontrib>Luque, M. Toledano</creatorcontrib><creatorcontrib>Parvais, B.</creatorcontrib><creatorcontrib>De Keersgieter, A.</creatorcontrib><creatorcontrib>Devriendt, K.</creatorcontrib><creatorcontrib>Van Ammel, A.</creatorcontrib><creatorcontrib>Schram, T.</creatorcontrib><creatorcontrib>Yoshida, N.</creatorcontrib><creatorcontrib>Phatak, A.</creatorcontrib><creatorcontrib>Han, K.</creatorcontrib><creatorcontrib>Colombeau, B.</creatorcontrib><creatorcontrib>Brand, A.</creatorcontrib><creatorcontrib>Horiguchi, N.</creatorcontrib><creatorcontrib>Thean, A. V.-Y</creatorcontrib><title>Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond</title><title>2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers</title><addtitle>VLSIT</addtitle><description>A scalable multi-V T enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-V T is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack T inv , J G , D IT and reliability as well as the device performance are shown to be unaffected by the multi V T process.</description><subject>Doping</subject><subject>FinFETs</subject><subject>Implants</subject><subject>Logic gates</subject><subject>Nitrogen</subject><subject>Tin</subject><issn>0743-1562</issn><isbn>9781479933310</isbn><isbn>1479933317</isbn><isbn>1479933325</isbn><isbn>1479933309</isbn><isbn>9781479933303</isbn><isbn>9781479933327</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2014</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1UMFOwzAUCwIktrEfgMv7gY6XJk2aIxqMTSriQLXrlKbpFtal05oO9cC_U4lxsi3LtmRCHijOKEX1tM4-V_ksRspnIlWcJeqKjCmXSjHG4uSaTJVM_zXFGzJCyVlEExHfkXHbfiHGmLB0RH6Wbrure2iNrnVRWyi6eg8L5xevObzYszO2hW8XdvDe1cFF6xyaY3CNb6HowTS-7ExwZwsHG3QNWx0stEGbPYTOO7-FqjlB2FmgGPkD-Ka0oH0Jhe2H7D25rXTd2ukFJyQfdufLKPt4W82fs8gpDFFaxLoQzFRYioFWtkIjaZUgQ1nKWHPFleQ81Ry50NQIbeTg6SKuRCo4YxPy-FfrrLWb48kd9KnfXJ5jvzC5YJs</recordid><startdate>201406</startdate><enddate>201406</enddate><creator>Ragnarsson, Lars-Ake</creator><creator>Chew, S. A.</creator><creator>Dekkers, H.</creator><creator>Luque, M. Toledano</creator><creator>Parvais, B.</creator><creator>De Keersgieter, A.</creator><creator>Devriendt, K.</creator><creator>Van Ammel, A.</creator><creator>Schram, T.</creator><creator>Yoshida, N.</creator><creator>Phatak, A.</creator><creator>Han, K.</creator><creator>Colombeau, B.</creator><creator>Brand, A.</creator><creator>Horiguchi, N.</creator><creator>Thean, A. V.-Y</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201406</creationdate><title>Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond</title><author>Ragnarsson, Lars-Ake ; Chew, S. A. ; Dekkers, H. ; Luque, M. Toledano ; Parvais, B. ; De Keersgieter, A. ; Devriendt, K. ; Van Ammel, A. ; Schram, T. ; Yoshida, N. ; Phatak, A. ; Han, K. ; Colombeau, B. ; Brand, A. ; Horiguchi, N. ; Thean, A. V.-Y</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-8b2ab63cf0d6b2afef0c71f50307d72a49497448a4046a1c6ac7030ab2f686433</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Doping</topic><topic>FinFETs</topic><topic>Implants</topic><topic>Logic gates</topic><topic>Nitrogen</topic><topic>Tin</topic><toplevel>online_resources</toplevel><creatorcontrib>Ragnarsson, Lars-Ake</creatorcontrib><creatorcontrib>Chew, S. A.</creatorcontrib><creatorcontrib>Dekkers, H.</creatorcontrib><creatorcontrib>Luque, M. Toledano</creatorcontrib><creatorcontrib>Parvais, B.</creatorcontrib><creatorcontrib>De Keersgieter, A.</creatorcontrib><creatorcontrib>Devriendt, K.</creatorcontrib><creatorcontrib>Van Ammel, A.</creatorcontrib><creatorcontrib>Schram, T.</creatorcontrib><creatorcontrib>Yoshida, N.</creatorcontrib><creatorcontrib>Phatak, A.</creatorcontrib><creatorcontrib>Han, K.</creatorcontrib><creatorcontrib>Colombeau, B.</creatorcontrib><creatorcontrib>Brand, A.</creatorcontrib><creatorcontrib>Horiguchi, N.</creatorcontrib><creatorcontrib>Thean, A. V.-Y</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ragnarsson, Lars-Ake</au><au>Chew, S. A.</au><au>Dekkers, H.</au><au>Luque, M. Toledano</au><au>Parvais, B.</au><au>De Keersgieter, A.</au><au>Devriendt, K.</au><au>Van Ammel, A.</au><au>Schram, T.</au><au>Yoshida, N.</au><au>Phatak, A.</au><au>Han, K.</au><au>Colombeau, B.</au><au>Brand, A.</au><au>Horiguchi, N.</au><au>Thean, A. V.-Y</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond</atitle><btitle>2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers</btitle><stitle>VLSIT</stitle><date>2014-06</date><risdate>2014</risdate><spage>1</spage><epage>2</epage><pages>1-2</pages><issn>0743-1562</issn><isbn>9781479933310</isbn><isbn>1479933317</isbn><eisbn>1479933325</eisbn><eisbn>1479933309</eisbn><eisbn>9781479933303</eisbn><eisbn>9781479933327</eisbn><abstract>A scalable multi-V T enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-V T is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack T inv , J G , D IT and reliability as well as the device performance are shown to be unaffected by the multi V T process.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2014.6894359</doi><tpages>2</tpages></addata></record>
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subjects Doping
FinFETs
Implants
Logic gates
Nitrogen
Tin
title Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T17%3A27%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Highly%20scalable%20bulk%20FinFET%20Devices%20with%20Multi-VT%20options%20by%20conductive%20metal%20gate%20stack%20tuning%20for%20the%2010-nm%20node%20and%20beyond&rft.btitle=2014%20Symposium%20on%20VLSI%20Technology%20(VLSI-Technology):%20Digest%20of%20Technical%20Papers&rft.au=Ragnarsson,%20Lars-Ake&rft.date=2014-06&rft.spage=1&rft.epage=2&rft.pages=1-2&rft.issn=0743-1562&rft.isbn=9781479933310&rft.isbn_list=1479933317&rft_id=info:doi/10.1109/VLSIT.2014.6894359&rft.eisbn=1479933325&rft.eisbn_list=1479933309&rft.eisbn_list=9781479933303&rft.eisbn_list=9781479933327&rft_dat=%3Cieee_CHZPO%3E6894359%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-8b2ab63cf0d6b2afef0c71f50307d72a49497448a4046a1c6ac7030ab2f686433%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6894359&rfr_iscdi=true