Mechanical stress management for electrical chip-package interaction (e-CPI)

e-CPI has emerged as a new risk in modern chip design as silicon dies become increasingly thinner and packages become increasingly more complex. e-CPI is different from traditional mechanical reliability related chip-package interaction, as it focuses on package stress impact on electrical circuit p...

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Bibliographic Details
Main Authors: Wei Zhao, Nakamoto, Mark, Ramachandran, Vidhya, Radojcic, Riko
Format: Conference Proceeding
Language:English
Subjects:
chip-package interaction
Integrated circuit modeling
mechanical stress
modeling
Piezoresistance
Random access memory
reliability
Semiconductor device modeling
Silicon
Stress
transistor mobility
Transistors
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Summary:e-CPI has emerged as a new risk in modern chip design as silicon dies become increasingly thinner and packages become increasingly more complex. e-CPI is different from traditional mechanical reliability related chip-package interaction, as it focuses on package stress impact on electrical circuit performance. A complete e-CPI modeling flow has been demonstrated. Both package FEA models and silicon piezoresistance coefficients are important for evaluating e-CPI risks. A case study of a product level circuit yield loss issue due to e-CPI has been discussed and modeled. The model has successfully reproduced the failure mechanism. Circuit designers, package designers, silicon foundries and package assembly houses should all take part in managing e-CPI risks.
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2014.6897447