Full custom implementation of a S-Box circuit architecture using power gated PLA structure

Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-Box), which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. Thi...

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Bibliographic Details
Main Authors: Ho Joon Lee, Yong-Bin Kim, Kyung Ki Kim
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Delays
Encryption
Hardware
Logic gates
Programmable logic arrays
Transistors
Online Access:Request full text
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Summary:Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-Box), which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. This paper presents a low power design of Rijndael S-Box for the SubByte transformation using power-gating and PLA design techniques to reduce area and leakage power during standby mode. The proposed design has been implemented using 0.11μm CMOS process with 1.2V power supply. The proposed design reduces the total leakage power and the total transistor count to 10% and 50% of the conventional design, respectively while improving the speed performance by ten times.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2014.6908410