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A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers
A digital built-in calibration (BIC) system is presented to automatically adjust the linearity performance of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digit...
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creator | Yongsuk Choi Chun-hsiang Chang Chauhan, Hari In-Seok Jung Onabajo, Marvin Yong-Bin Kim |
description | A digital built-in calibration (BIC) system is presented to automatically adjust the linearity performance of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. The output of the envelope detector is digitized before the spectrum calculation with an integrated fast Fourier transform (FFT) for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total calibration time is 485μs. The digital blocks were implemented using a standard 0.13μm CMOS technology. |
doi_str_mv | 10.1109/MWSCAS.2014.6908486 |
format | conference_proceeding |
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An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. The output of the envelope detector is digitized before the spectrum calculation with an integrated fast Fourier transform (FFT) for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total calibration time is 485μs. The digital blocks were implemented using a standard 0.13μm CMOS technology.</description><subject>analog/RF testing</subject><subject>built-in calibration (BIC)</subject><subject>Calibration</subject><subject>Capacitors</subject><subject>Engines</subject><subject>envelope detection</subject><subject>Envelope detectors</subject><subject>fast Fourier transform (FFT)</subject><subject>Linearity</subject><subject>linearization</subject><subject>Low-noise amplifier (LNA)</subject><subject>Radio frequency</subject><subject>spectral analysis</subject><subject>System-on-chip</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>9781479941346</isbn><isbn>1479941344</isbn><isbn>1479941328</isbn><isbn>9781479941322</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2014</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kF1LwzAYheMXuM39gt3kD7QmzUeTyzKcChPBKV6OtHmDkbYpaXYxf72VzZtz4DyHF96D0IqSnFKi718-d-tqlxeE8lxqoriSF2hOeak1p6xQl2hGhVAZU1pfoaUu1T_j8vqP8YmVXN6i-Th-E1KwkuoZqitcH3ybMt_jxrS-jib50OPxOCbocAo4DMl3_gdw-vLRZiFaiNj3CWIX7KE91QeILsTO9A3g4PDbBptuaL3zEMc7dONMO8Ly7Av0sXl4Xz9l29fH53W1zXxBVMq41tLU1pba1MQ0VBJgglihai3LSRwYEILaQrjp90ZoZaQCANkwx6kFtkCr010_pfsh-s7E4_68FfsF2D1cRg</recordid><startdate>20140801</startdate><enddate>20140801</enddate><creator>Yongsuk Choi</creator><creator>Chun-hsiang Chang</creator><creator>Chauhan, Hari</creator><creator>In-Seok Jung</creator><creator>Onabajo, Marvin</creator><creator>Yong-Bin Kim</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20140801</creationdate><title>A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers</title><author>Yongsuk Choi ; Chun-hsiang Chang ; Chauhan, Hari ; In-Seok Jung ; Onabajo, Marvin ; Yong-Bin Kim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i208t-4996abdd79ab0ac160e350d58b9678b9feae551d25f486c598a68eee6c3f41de3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2014</creationdate><topic>analog/RF testing</topic><topic>built-in calibration (BIC)</topic><topic>Calibration</topic><topic>Capacitors</topic><topic>Engines</topic><topic>envelope detection</topic><topic>Envelope detectors</topic><topic>fast Fourier transform (FFT)</topic><topic>Linearity</topic><topic>linearization</topic><topic>Low-noise amplifier (LNA)</topic><topic>Radio frequency</topic><topic>spectral analysis</topic><topic>System-on-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Yongsuk Choi</creatorcontrib><creatorcontrib>Chun-hsiang Chang</creatorcontrib><creatorcontrib>Chauhan, Hari</creatorcontrib><creatorcontrib>In-Seok Jung</creatorcontrib><creatorcontrib>Onabajo, Marvin</creatorcontrib><creatorcontrib>Yong-Bin Kim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yongsuk Choi</au><au>Chun-hsiang Chang</au><au>Chauhan, Hari</au><au>In-Seok Jung</au><au>Onabajo, Marvin</au><au>Yong-Bin Kim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers</atitle><btitle>2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)</btitle><stitle>MWSCAS</stitle><date>2014-08-01</date><risdate>2014</risdate><spage>599</spage><epage>602</epage><pages>599-602</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>9781479941346</isbn><isbn>1479941344</isbn><eisbn>1479941328</eisbn><eisbn>9781479941322</eisbn><abstract>A digital built-in calibration (BIC) system is presented to automatically adjust the linearity performance of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. The output of the envelope detector is digitized before the spectrum calculation with an integrated fast Fourier transform (FFT) for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total calibration time is 485μs. The digital blocks were implemented using a standard 0.13μm CMOS technology.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2014.6908486</doi><tpages>4</tpages></addata></record> |
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subjects | analog/RF testing built-in calibration (BIC) Calibration Capacitors Engines envelope detection Envelope detectors fast Fourier transform (FFT) Linearity linearization Low-noise amplifier (LNA) Radio frequency spectral analysis System-on-chip |
title | A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers |
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