A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer

This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms o...

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Bibliographic Details
Main Authors: Peng Zhu, Xinpeng Xing, Gielen, Georges
Format: Conference Proceeding
Language:English
Subjects:
Adders
Bandwidth
Power harmonic filters
Prototypes
Signal to noise ratio
Topology
Online Access:Request full text
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Summary:This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2014.6942022