An ultra-low-voltage all-digital PLL for energy harvesting applications

A 2 GHz all-digital phase locked loop (ADPLL) with core components operating from a 300-mV supply is presented. Ultra-low voltage frequency division and phase/frequency quantization are performed by a ring oscillator that is superharmonically injection-locked to the digitally-controlled oscillator (...

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Bibliographic Details
Main Authors: Silver, Jason, Sankaragomathi, Kannan, Otis, Brian
Format: Conference Proceeding
Language:English
Subjects:
CMOS integrated circuits
Frequency conversion
Frequency measurement
Noise measurement
Phase measurement
Phase noise
Radio frequency
Online Access:Request full text
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Summary:A 2 GHz all-digital phase locked loop (ADPLL) with core components operating from a 300-mV supply is presented. Ultra-low voltage frequency division and phase/frequency quantization are performed by a ring oscillator that is superharmonically injection-locked to the digitally-controlled oscillator (DCO). An injection-locking technique is proposed which facilitates locking with no additional active devices, minimizing capacitive loading and maximizing the oscillation frequency of the divider at low voltage. The ADPLL is fabricated in a 65-nm CMOS process, and consumes a total of 780 μW, 720μW from a 300-mV supply (V DDL ) and 60μW from a 600-mV supply (V DDH ).
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2014.6942029