HTOL SRAM Vmin shift considerations in scaled HKMG technologies

This paper examines the role of NBTI and PBTI on SRAM Vmin shifts during HTOL stressing and quantifies their impact on reliability lifetime projections in scaled high-k metal gate (HKMG) technologies. Correlation between measured HTOL SRAM Vmin shifts and transistor level parametrics is summarized o...

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Bibliographic Details
Main Authors: Balasubramanian, S., Joshi, V., Klick, T., Mann, R., Versaggi, J., Gautam, A., Weintraub, C., Kurz, G., Krause, G., Kerber, A., Parameshwaran, B., Nigam, T.
Format: Conference Proceeding
Language:English
Subjects:
CMOS
Correlation
Degradation
HKMG
HTOL
Logic gates
NBTI
PBTI
Random access memory
Reliability
replacement metal gate
scaling
SRAM
Stress
Transistors
Vmin
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Summary:This paper examines the role of NBTI and PBTI on SRAM Vmin shifts during HTOL stressing and quantifies their impact on reliability lifetime projections in scaled high-k metal gate (HKMG) technologies. Correlation between measured HTOL SRAM Vmin shifts and transistor level parametrics is summarized on both 28nm poly-SiON and HKMG technologies. The paper concludes that the commonly used HTOL acceleration voltage of 1.4xVnom may be excessive in scaled HKMG technologies due to the larger role of PBTI in SRAMs.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2014.6946031