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A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques
The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comp...
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| creator | Keunsoo Song Sangkwon Lee Dongkyun Kim Youngbo Shim Sangil Park Bokrim Ko Duckhwa Hong Yongsuk Joo Wooyoung Lee Yongdeok Cho Wooyeol Shin Jaewoong Yun Hyengouk Lee Jeonghun Lee Eunryeong Lee Jaemo Yang Haekang Jung Namkyu Jang Joohwan Cho Hyeongon Kim Jinkook Kim |
| description | The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comparing with that of LPDDR3. This works includes various techniques including multi-channel per die, various trainings, low swing interface, DQS and clock frequency dividing, internal reference voltage for data and command-address signals and so on. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process. |
| doi_str_mv | 10.1109/CICC.2014.6946032 |
| format | conference_proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0886-5930 |
| ispartof | Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, p.1-4 |
| issn | 0886-5930 2152-3630 |
| language | eng |
| recordid | cdi_ieee_primary_6946032 |
| source | IEEE Xplore All Conference Series |
| subjects | Bandwidth Clocks Computer aided software engineering DRAM dram interface Frequency conversion LPDDR4 memory architecture Random access memory Timing Training |
| title | A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques |
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