A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled os...

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Bibliographic Details
Main Authors: Joung-Wook Moon, Sung-Geun Kim, Dae-Hyun Kwon, Woo-Young Choi
Format: Conference Proceeding
Language:English
Subjects:
Automatic frequency calibration (AFC)
charge pump
Charge pumps
Current measurement
current mismatch
current variation
Frequency control
Frequency measurement
near-threshold voltage (NTV)
Phase locked loops
phase-locked loop (PLL)
ultra-low power
ultra-low voltage (ULV)
Voltage control
Voltage-controlled oscillators
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Description
Summary:We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2014.6946100