Design of low power differential conditional capturing flip-flop

The operation of low/full swing LC resonant clocking scheme helps in reducing the overall power of the system by introducing a modern new flip-flop. The proposed dual mode low/full-swing differential conditional capturing flip-flop (LF-CCFF) operates with a low/full-swing sinusoidal clock through th...

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Bibliographic Details
Main Authors: Kasiselvanathan, M., Saranya, P., Lakshmi, A. Seetha, Sivasakthi, S.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Clocks
Conferences
Flip-flop
Flip-flops
Full swing
Inverters
low swing
power
Power demand
Synchronization
Online Access:Request full text
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Summary:The operation of low/full swing LC resonant clocking scheme helps in reducing the overall power of the system by introducing a modern new flip-flop. The proposed dual mode low/full-swing differential conditional capturing flip-flop (LF-CCFF) operates with a low/full-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The LF-CCFF reduces the power consumption compared to the single mode full-swing flip-flop. The power has been obtained by using 180-nm CMOS technology. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low/full-swing sinusoidal clock has been characterized. The LF-CCFF has compared to the full-swing flip-flop both having the same setup time for a 100 MHz sinusoidal clock.
DOI:10.1109/ICCTET.2014.6966293