Energy efficiency improvement of renamed trace cache through the reduction of dependent path length

A renaming logic is a high-cost module in a superscalar processor, and it consumes significant energy. For mitigating this, renamed trace cache (RTC), which caches renamed operands, was proposed. However, conventional RTCs have several problems such as low capacity-efficiency, large hardware overhea...

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Bibliographic Details
Main Authors: Shioya, Ryota, Ando, Hideki
Format: Conference Proceeding
Language:English
Subjects:
Arrays
Energy consumption
Hardware
Pipelines
Proposals
Random access memory
Registers
Online Access:Request full text
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Summary:A renaming logic is a high-cost module in a superscalar processor, and it consumes significant energy. For mitigating this, renamed trace cache (RTC), which caches renamed operands, was proposed. However, conventional RTCs have several problems such as low capacity-efficiency, large hardware overhead and insufficient caching of renamed operands. We propose a semi-global renamed trace cache (SGRTC) that caches only renamed operands whose distances from producers outside traces are short, and it solves the problems of conventional RTCs. Evaluation results show that SGRTC achieves 64% lower energy consumption for renaming with a 0.2% performance overhead compared to a conventional processor.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2014.6974714