A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13- \mu m CMOS Technology

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2015-11, Vol.23 (11), p.2671-2675
• Main Authors: Chu, Myonglae, Kim, Byoungho, Lee, Byung-Geun
• Format: Article
• Language: English
• Subjects: Amplifiers; Analog-to-digital converter (ADC); Architecture (computers); Bandwidth; CMOS; CMOS integrated circuits; digital error correction; Dissipation; Interpolation; Nonlinearity; open-loop (OL) amplifier; pipeline ADC; Pipelines; Sampling; Solid state circuits; Switches; Very large scale integration; zero-crossing detection
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2371453

This brief presents a zero-crossing-based pipeline analog-todigital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13-μm CMOS process and occupies a die area of 0.7 mm2. The differential and integral nonlinearity of the ADC are less than 0.83/-0.47 and 1.05/-0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.