A 30-Gb/s 1.37-pJ/b CMOS Receiver for Optical Interconnects

• Published in: Journal of lightwave technology 2015-02, Vol.33 (4), p.778-786
• Main Authors: Quan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Yan Lu, Wing-Hung Ki, Chiang, Patrick, Yue, C. Patrick
• Format: Article
• Language: English
• Subjects: Bandwidth; cascaded continuous-time linear equalizer; CMOS integrated circuits; Connectors; Gain; limiting amplifier; Noise; offset cancellation; Optical receiver; Optical receivers; output driver; transimpedance amplifier
• ISSN: 0733-8724; 1558-2213
• DOI: 10.1109/JLT.2014.2381266

This paper presents a digitally controlled 1-V 30-Gb/s 1.37-pJ/b optical receiver in 65-nm CMOS technology. This receiver consists of an inverter-based inductive transimpedance amplifier, a fully integrated low-dropout regulator, a main amplifier, a three-stage-cascaded continuous-time linear equalizer (CTLE), a two-stage limiting amplifier, and an output driver. The CTLE consists of three cascaded stages with different peaking frequencies (5, 12, and 20 GHz) offering 16 dB of adjustable low-frequency gain to accommodate different photodetector (PD) characteristics. The electrical measurements demonstrate a maximum transimpedance gain of 83 dBΩ (14,125 Ω), an output swing of 300 mV, a -3-dB bandwidth of 24 GHz, and a power consumption of 41 mW. Moreover, optical measurement results with a 28-Gb/s PD show that the receiver achieves 10 -12 BER at 30 Gb/s for a 2 15 -1 PRBS input with a -5.6-dBm input sensitivity. Using a lower bandwidth 14-Gb/s PD, the receiver can still reach 30 Gb/s at 10 -12 BER with only a 0.6-dB degradation in input sensitivity, demonstrating the effectiveness of the proposed receiver and the programmable-cascaded CTLE. The core area occupies 0.26 mm 2 .