Computation-skip error resilient scheme for recursive CORDIC

Aggressive voltage and frequency scaling are widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical voltage or frequency results to numerous timing errors, and hence unacceptable output quality. In this paper,...

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Bibliographic Details
Main Authors: Yanxiang Huang, Meng Li, Chunshu Li, Debacker, Peter, Van der Perre, Liesbet
Format: Conference Proceeding
Language:English
Subjects:
Approximation methods
Clocks
Energy consumption
Hardware
Latches
Monitoring
Timing
Online Access:Request full text
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Summary:Aggressive voltage and frequency scaling are widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical voltage or frequency results to numerous timing errors, and hence unacceptable output quality. In this paper, a computation-skip (CS) scheme is proposed for recursive digital signal processors with a fixed cycles per instruction (CPI) to correct timing errors. A CORDIC processor with the proposed CS scheme still functions when scaling beyond the sub-critical voltage or frequency. It improves EVM by 47.9 dB at its most critical frequency or supply voltage, and extends the voltage scaling limit by 90 mV w.r.t the conventional CORDIC. Besides, it is more than 1.7X energy efficient w.r.t. the conventional high-speed CORDIC, which is designed for a more aggressive scaling.
ISSN:2162-3562
2162-3570
DOI:10.1109/SiPS.2014.6986061