High efficiency class E power amplifier with drain source merging technique

This paper studies the effects of different cell-based layout styles of cascode class-E power amplifiers (PAs) in 0.18-μm TSMC CMOS technology. Different types of layouts for PA cascode transistors are investigated. Merging technique for the PA cascode transistors is introduced that reduces the auxi...

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Bibliographic Details
Main Authors: Padash, Mohsen, Dehqan, Ali, Yargholi, Mostafa, Toofan, Siroos
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Capacitors
class-E power amplifier (PA)
CMOS integrated circuits
high efficiency
Layout
Merging
merging technique
Power amplifiers
RFID
Transistors
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Summary:This paper studies the effects of different cell-based layout styles of cascode class-E power amplifiers (PAs) in 0.18-μm TSMC CMOS technology. Different types of layouts for PA cascode transistors are investigated. Merging technique for the PA cascode transistors is introduced that reduces the auxiliary shunt capacitors of cascode transistors. As a result, total power dissipation of class E PA is reduced and its efficiency is improved. To demonstrate it applicability, the design of a state-of-the-art 1.8-GHz differential cascode class E PA is presented. At 23-dBm output power, a power added efficiency (PAE) as high as 33% for the merging technique and 31% for conventional cascode transistors, was obtained from postlayout simulation with 1.8 V supply.
ISSN:2164-7054
DOI:10.1109/IranianCEE.2014.6999598