Simulation analysis of the Control Point Policy for semiconductor fab lines producing multiple part types

• Main Authors: Liaqat, Talha, Young Jae Jang
• Format: Conference Proceeding
• Language: English
• Subjects: Fabrication; Job shop scheduling; Load modeling; Semiconductor device modeling; Workstations
• ISSN: 0891-7736; 1558-4305
• DOI: 10.1109/WSC.2014.7020097

In this paper, we introduce a new modified version of the scheduling approach, Control Point Policy (CPP) for semiconductor wafer fabrication lines and compare its performance with the popular Earliest Due Date (EDD), Minimum Slack (MS) and Critical Ratio (CR) scheduling policies. Discrete event modeling and simulations are created to evaluate the performance of CPP for three important performance measures; cycle times, waiting times and inventory levels. New insights for system performance are developed with the implementation of CPP at bottleneck stations and the introduction of finite size buffers between all the workstations. Our simulation results demonstrate the ability of CPP to achieve lowest cycle times with minimum inventory levels for situations where products with similar process characteristics are prioritized over each other. Our simulation experiments show that the CPP generates good system performance for environments where multiple products at different processing stages compete for limited resources.