A scalable architecture for implementing the fast discrete periodic radon transform for prime sized images

• Main Authors: Carranza, Cesar, Llamocca, Daniel, Pattichis, Marios
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Clocks; Computer architecture; Discrete Periodic Radon Transform (DPRT); Field programmable gate arrays; FPGA; Hardware; Parallel Architecture; Scalable Architecture; Strips; Transforms; VLSI
• ISSN: 1522-4880; 2381-8549
• DOI: 10.1109/ICIP.2014.7025241

The Discrete Periodic Radon Transform (DPRT) has many important applications in image processing that are associated with reconstructing objects from projections (e.g., computed tomography [1]) or image restoration (e.g., [2]). Thus, there is strong interest in the development of fast algorithms and architectures for computing the DPRT. This paper introduces a scalable hardware architecture and associated algorithm for computing the DPRT for prime-sized images. For square images of size N × N, N prime, the DPRT requires N 2 (N - 1) additions for calculating image projections along a minimal number of prime directions. The proposed approach can compute the DPRT in [N/2 h ] N + 2N + h clock cycles, h = 1, ..., [log 2 N], where h is a scaling factor that is used to control the required hardware resources that are needed to implement the fast DPRT. Compared to previous approaches, a fundamental contribution of the proposed architecture is that it allows effective implementations based on different constraints on the resources.