An ultra-low power consumption and very compact 1.49 GHz CMOS Voltage Controlled Ring Oscillator

In this paper, a three-stage Voltage Controlled Ring Oscillator, designed and implemented using IBM 130nm CMOS technology with Cadence Virtuoso tools, is presented. The initial specification for the output frequency is 400MHz-1GHz, but our proposed design could generate the oscillation range from 82...

Full description

Saved in:
Bibliographic Details
Main Authors: Duc Xuan Tran, Trinh Trong Dang
Format: Conference Proceeding
Language:English
Subjects:
CMOS
compact layout
Frequency control
Inverters
Layout
low power
phase noise
ring oscillator
Transistors
VCO
Voltage control
Voltage-controlled oscillators
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, a three-stage Voltage Controlled Ring Oscillator, designed and implemented using IBM 130nm CMOS technology with Cadence Virtuoso tools, is presented. The initial specification for the output frequency is 400MHz-1GHz, but our proposed design could generate the oscillation range from 82.72KHz to 1.49GHz when control voltage is from 0.0V to 1.2V. Furthermore, the power consumption is extremely low 30.5 uW at 1GHz and the layout is very compact with an active area of 42.3um 2 . Besides that, the phase noise is -101.33 dB/Hz at 1MHz offset from 1.37 MHz center frequency. Comparisons with existing VCO designs show a big improvement of our design in terms of power consumption and area.
ISSN:2162-1020
2162-1039
DOI:10.1109/ATC.2014.7043391