A Programmable 0.7-2.7 GHz Direct \Delta \Sigma Receiver in 40 nm CMOS

This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A f...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2015-03, Vol.50 (3), p.644-655
Main Authors: Englund, Mikko, Ostman, Kim B., Viitala, Olli, Kaltiokallio, Mikko, Stadius, Kari, Koli, Kimmo, Ryynanen, Jussi
Format: Article
Language:English
Subjects:
Baseband
Blocker filtering
continuous-time
delta-sigma modulation
direct conversion receivers
direct delta-sigma receiver
frequency-translating
Gain
N-path filtering
Noise
noise shaping
Quantization (signal)
Radio frequency
Receivers
RF sampling
Wideband
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Summary:This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2015.2397193