High density, low cost packaging and interconnect technology

The increase of I/O on chip is driving chip, package and board interconnect schemes to alternative technologies. Area array flip chips and BGAs are beginning to replace peripheral pad limited chips and tight pitch leads on PQFPs. The PWB industry is looking at technologies which form "microvias...

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Bibliographic Details
Main Author: Garrou, P.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Bonding
Capacitive sensors
Chemical technology
Costs
Driver circuits
Electronics industry
Flip chip
Logic devices
Packaging
Online Access:Request full text
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Summary:The increase of I/O on chip is driving chip, package and board interconnect schemes to alternative technologies. Area array flip chips and BGAs are beginning to replace peripheral pad limited chips and tight pitch leads on PQFPs. The PWB industry is looking at technologies which form "microvias" to handle the interconnection of these high density chip/package formats. New technologies such as large area processing (LAP) and seamless high off chip connectivity (SHOCC) are being developed to meet these needs.
DOI:10.1109/IEMTIM.1998.704499