Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing

Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This p...

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Bibliographic Details
Main Authors: Tripathy, Suryasnata, Omprakash, L. B., Mandal, Sushanta K., Patro, B. S.
Format: Conference Proceeding
Language:English
Subjects:
Adders
CMOS
Computer architecture
Delays
High speed
Logic gates
Low power
Power demand
Topology
Transistors
Urdhva Tiryakbhyam
Vedic multiplier
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Summary:Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Process technology using Cadence EDA tool.
DOI:10.1109/ICCICT.2015.7045662