Ultra low contact resistivity (−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III-V fin TLM structure fabricated with III-V on Si substrates

• Main Authors: Lee, Rinus T. P., Ohsawa, Y., Huffman, C., Trickett, Y., Nakamura, G., Hatem, C., Rao, K. V., Khaja, F., Lin, R., Matthews, K., Dunn, K., Jensen, A., Karpowicz, T., Nielsen, Peter F., Stinzianni, E., Cordes, A., Hung, P. Y., Kim, D-H, Hill, R. J. W., Loh, W-Y, Hobbs, C.
• Format: Conference Proceeding
• Language: English
• Subjects: Implants; Metals; Resistance; Rough surfaces; Silicon; Surface roughness; Surface treatment
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2014.7047155

We report a record low contact resistivity of sub-1.0×10 -8 Ω.cm 2 realized on n + In 0.53 Ga 0.47 As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to eliminate implant damage in III-V fins. This increased activation efficiency (+3.6×) and reduced sheet resistance (-60%).