Research of electroplating and electroless plating for low temperature bonding in 3D heterogeneous integration

In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270°C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn μ-bumps are electroplated on common technology node and ENIG...

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Bibliographic Details
Main Authors: Yu-Chen Hu, Yao-Jen Chang, Chun-Shen Wu, Yung Mao Cheng, Wei Jen Chen, Kuan-Neng Chen
Format: Conference Proceeding
Language:English
Subjects:
Bonding
Gold
Integrated circuits
Joints
Scanning electron microscopy
Three-dimensional displays
Tin
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Summary:In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270°C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn μ-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 μm bump pitch, 40 μm diameter of Cu/Sn μ-bump and 50 μm diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.
ISSN:2150-5934
2150-5942
DOI:10.1109/IMPACT.2014.7048426