Charge trap length dependence and transconductance characteristics of a 2T SONOS cell

• Main Authors: Tae-Ho Lee, Young-Jun Kwon, Jae-Gwan Kim, Sung-Kun Park, In-Wook Cho, Kyung-Dong Yoo, Ji-Song Lim, Da-Som Kim, Woo Young Choi, Gyu-Han Yoon
• Format: Conference Proceeding
• Language: English
• Subjects: BTBT-HHI; CHEI; Electron traps; embedded NVM; Junctions; Logic gates; mismatch; Nonvolatile memory; Programming; SONOS; SONOS devices
• DOI: 10.1109/NVMTS.2014.7060859

In this paper, the program and erase characteristics of a two-transistor (2T) SONOS nonvolatile memory (NVM) cell have been described by using one-shot simulations and device simulations. In addition, a mismatched charge distribution between electrons and holes has been verified through measurements and device simulations. The program and erase (P/E) operations are performed through channel hot electron injection (CHEI) and band to band tunneling induced hot hole injection (BTBT-HHI), respectively. Because a complete erase operation can't be achieved with longer control gate (CG) lengths, the optimized CG length is a key factor in the 2T SONOS device. The proposed cell uses the whole channel to achieve good reliability during the program and erase operations. Nevertheless, it is strongly suspected that excess electrons might gradually build up in the nitride layer toward the source junction because of spatial mismatches of the injected electrons and holes during P/E cycles. This phenomenon of electron build-up has been confirmed through both device simulations and real measurements of the gate length dependence of the program and erase speeds. As a result of gradual accumulation of electrons, the cell transconductance (G m ) continues to become reduced. The degraded G m value is also observed to be noticeably improved after a process of bake retention.