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13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network

In previous research, solutions to the requirements for BLE have been widely discussed such as using the sliding IF (SIF) architecture in the RX [1,2] and a Class-D amplifier [2] with HD2 calibration [4] in the TX to achieve lower current consumption. The SIF architecture, however, involves RF image...

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Main Authors: Sano, Tomohiro, Mizokami, Masakazu, Matsui, Hiroaki, Ueda, Keisuke, Shibata, Kenichi, Toyota, Kenji, Saitou, Tatsuhito, Sato, Hisayasu, Yahagi, Koichi, Hayashi, Yoshihiro
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creator Sano, Tomohiro
Mizokami, Masakazu
Matsui, Hiroaki
Ueda, Keisuke
Shibata, Kenichi
Toyota, Kenji
Saitou, Tatsuhito
Sato, Hisayasu
Yahagi, Koichi
Hayashi, Yoshihiro
description In previous research, solutions to the requirements for BLE have been widely discussed such as using the sliding IF (SIF) architecture in the RX [1,2] and a Class-D amplifier [2] with HD2 calibration [4] in the TX to achieve lower current consumption. The SIF architecture, however, involves RF image blocking violation without exception rule or the use of additional off-chip filters. In the TX, meanwhile, the calibration incurs a weakness in terms of the offset issue. Moreover, there is no approach to achieve "zero" external components for the RF port. In this paper, a BLE transceiver, with a reconfigurable filter, embedded into an on-chip matching network without any external components, is presented.
doi_str_mv 10.1109/ISSCC.2015.7063015
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identifier ISSN: 0193-6530
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2376-8606
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Architecture
Calibration
Consumption
Devices
Matched filters
Matching
Networks
Phase locked loops
Power harmonic filters
Radio frequency
Smartphones
System-on-chip
Transceivers
title 13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network
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