Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

• Published in: IEEE transactions on electron devices 2015-06, Vol.62 (6), p.1754-1759
• Main Authors: Hanwool Jeong, Younghwi Yang, Seung Chul Song, Wang, Joseph, Yeap, Geoffrey, Seong-Ook Jung
• Format: Article
• Language: English
• Subjects: Circuit synthesis; CMOS integrated circuits; Delays; Energy consumption; Energy-delay product (EDP); figure of merit (FOM); Inverters; near-threshold-voltage circuit design; System-on-chip; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2015.2424220

A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (V th ) region, where the supply voltage (V DD ) is slightly higher than V th . When V DD is scaled down to near V th , the drain current becomes greatly sensitive to V DD or V th ; furthermore, the energy exhibits the same sensitivity as that in the super-V th region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-V th region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-V th and near-V th regions, which verifies that the proposed FOM is appropriate in the near-V th region, whereas the EDP is not.