Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

• Main Authors: Palermo, N., Tihhomirov, V., Copetti, T. S., Jenihhin, M., Raik, J., Kostin, S., Gaudesi, M., Squillero, G., Sonza Reorda, M., Vargas, F., Bolzani Poehls, L.
• Format: Conference Proceeding
• Language: English
• Subjects: Aging; critical path identification; Degradation; Delays; Evolutionary computation; hardware rejuvenation; logic circuit; Logic gates; MicroGP; MOSFET; Nanoscale devices; NBTI; zamiaCAD
• ISSN: 2373-0862
• DOI: 10.1109/LATW.2015.7102405

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the threshold voltage of pMOS transistors, which slows down signal propagation along the paths between flip-flops. As a consequence, NBTI may cause transient faults and, ultimately, permanent circuit functional failure. In this paper, we propose an innovative NBTI mitigation approach by rejuvenation of nanoscale logic along NBTI-critical paths. The method is based on hierarchical NBTI-critical paths identification and rejuvenation stimuli generation using an Evolutionary Algorithm. The rejuvenation stimuli are used to drive to the recovery phase the pMOS transistors that are the most significant for the NBTI-induced path delay. This rejuvenation procedure is to be applied to the circuit as an execution overhead at predefined periods. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics. Experimental results are demonstrated by electrical simulations of an ALU circuit design.