FPGA based DSC-PLL for grid harmonics and voltage unbalance effect elimination

• Main Authors: Jongmin Jo, Byung-Moon Han, Hanju Cha
• Format: Conference Proceeding
• Language: English
• Subjects: Field programmable gate arrays; Generators; Hardware design languages; Harmonic analysis; Harmonic distortion; Phase locked loops; Power system harmonics
• ISSN: 1048-2334; 2470-6647
• DOI: 10.1109/APEC.2015.7104656

In this paper, the design of DSC-PLL (Delayed Signal Cancellation Phase Locked Loop) based on FPGA is discussed. This method shows outstanding performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid harmonics and voltage unbalance. The harmonic elimination technique of DSC is analyzed and DSC-PLL method is implemented on FPGA with a discrete fixed point based. Process for FPGA design is investigated and DSC-PLL is designed by system generator compatible with MATLAB/SIMULINK, by which schematic is directly converted to HDL (Hardware Descriptions Language) and then programmed into the FPGA. To verify the performance of the FPGA based DSC-PLL and conventional SRF-PLL, two methods are implemented on XC7Z030 and are tested under distorted three-phase voltage conditions respectively. The results show the SRF-PLL contains continuous oscillations with harmonic influence, but the proposed FPGA based DSC-PLL perfectly eliminates any harmonics within maximum 5.44ms and detects the fundamental positive sequence successfully under distorted three-phase voltage.