Board level reliability enhancements for wafer level package

This paper investigates the enhancement of Wafer Level Package (WLP) solder reflow process to reduce the negative impacts on Board Level Reliability (BLR) and to accommodate the 3-layer WLP. Using SAC405 solder alloy, we fine tune the reflow profile and minimize the formation of the brittle Intermet...

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Bibliographic Details
Main Authors: Qiao, John, Wenwen He, Yang, Kelly, Chien, Wei-Ting Kary
Format: Conference Proceeding
Language:English
Subjects:
Board level reliability
Foundries
High speed ball shear
Intermetallic compound
Polymers
Semiconductor device reliability
Soldering
Temperature measurement
Wafer level package
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Summary:This paper investigates the enhancement of Wafer Level Package (WLP) solder reflow process to reduce the negative impacts on Board Level Reliability (BLR) and to accommodate the 3-layer WLP. Using SAC405 solder alloy, we fine tune the reflow profile and minimize the formation of the brittle Intermetallic Compound (IMC) that is positive for BL R Drop Test (DT). We find that High Speed Ball Shear (HSBS) is a good and simple measurement to evaluate the solder joint performance during BLR DT. Furthermore, we recommended a BLR characterization procedure under wafer foundry turnkey mode and demonstrated the advantages of the turnkey mode with an example of how a foundry proactively leads bumping subcontractors to effectively solve chip and packaged interaction problems.
ISSN:0149-144X
2577-0993
DOI:10.1109/RAMS.2015.7105070