Transistor aging and reliability in 14nm tri-gate technology

This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. This technology introduces Intel's 2 nd generation tri-gate transistor and the 4 th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highl...

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Bibliographic Details
Main Authors: Novak, S., Parker, C., Becher, D., Liu, M., Agostinelli, M., Chahal, M., Packan, P., Nayak, P., Ramey, S., Natarajan, S.
Format: Conference Proceeding
Language:English
Subjects:
14nm
Bias Temperature Instability
Degradation
Fin-FET
High-k
Hot carriers
Integrated circuit reliability
Logic gates
metal gate
Oxide Breakdown
Stress
Transistors
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Summary:This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. This technology introduces Intel's 2 nd generation tri-gate transistor and the 4 th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2015.7112692