Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate

From the experimental measurements, the dominant charge source for a packaged IC chip during a charged-device model (CDM) ESD event is the capacitor between the die-attach plate and the metal bus line, C SUB . By adding a bonding wire between the die-attach plate and the Vss pin, a parallel inductor...

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Bibliographic Details
Main Authors: Tzu-Cheng Kao, Jian-Hsing Lee, Chen-Hsin Lien, Chih-Hsien Wang, Kuang-Cheng Tai, Hung-Der Su
Format: Conference Proceeding
Language:English
Subjects:
Bonding
Capacitance
Charged device model (CDM)
Discharges (electric)
Electrostatic-discharge (ESD)
Integrated circuit modeling
RLC circuits
Silicon on insulator (SOI)
Wires
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Description
Summary:From the experimental measurements, the dominant charge source for a packaged IC chip during a charged-device model (CDM) ESD event is the capacitor between the die-attach plate and the metal bus line, C SUB . By adding a bonding wire between the die-attach plate and the Vss pin, a parallel inductor to the C SUB can be created. The CDM-robustness for the packaged IC chip is significantly improved because of this parallel LC resonance circuit.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2015.7112797