RTS noise reduction of 1Y-nm floating gate NAND flash memory using process optimization

We report the random telegraph noise characteristics of 1Y-nm floating gate NAND Flash memory and behaviors of random telegraph noise generating traps. The location of selected traps are extracted and their behaviors in different temperature are also investigated. To reduce the threshold voltage flu...

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Bibliographic Details
Main Authors: Sungho Kim, Myeongwon Lee, Gil-Bok Choi, Jaekwan Lee, Yunbong Lee, Myoungkwan Cho, Kun-Ok Ahn, Jinwoong Kim
Format: Conference Proceeding
Language:English
Subjects:
Electron traps
Flash memories
Fluctuations
Noise
Nonvolatile memory
Optimization
Random telegraph noise
Temperature measurement
Threshold voltage fluctuations
Trap behaviors
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Summary:We report the random telegraph noise characteristics of 1Y-nm floating gate NAND Flash memory and behaviors of random telegraph noise generating traps. The location of selected traps are extracted and their behaviors in different temperature are also investigated. To reduce the threshold voltage fluctuations, we optimize the process conditions of 1Y-nm floating gate NAND Flash memories including tunnel oxide reduction and modification on annealing conditions. We successfully decrease the threshold voltage fluctuations as low as that of 2Y-nm floating gate NAND Flash memories.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2015.7112811