A Compact Test Structure for Characterizing Transistor Variability Beyond 3\sigma

An addressable array test structure is proposed for characterization of transistor variability beyond 3σ away from the mean. The design of the array is based on very compact basic cells which enable a highly efficient layout which has over three times higher normalized device density than similar ar...

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Bibliographic Details
Published in:IEEE transactions on semiconductor manufacturing 2015-08, Vol.28 (3), p.329-336
Main Authors: Chen, Christopher S., Liping Li, Lim, Queennie, Hong HaiTeh, Binti Omar, Noor Fadillah, Chun-Lee Ler, Watt, Jeffrey T.
Format: Article
Language:English
Subjects:
Arrays
Current measurement
Decoding
Logic gates
measurement
MOSFETs
Semiconductor device measurement
statistics
Transistors
variability
Voltage measurement
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Summary:An addressable array test structure is proposed for characterization of transistor variability beyond 3σ away from the mean. The design of the array is based on very compact basic cells which enable a highly efficient layout which has over three times higher normalized device density than similar arrays. Implementations of a 32k array are demonstrated for placement in a standard wafer scribe lane module. Characterization results based on an advanced high-k/metal gate process show that transistor threshold voltages follow a Gaussian distribution at current levels typically used in digital circuits. Analysis of random and systematic components of variability confirms that there are no systematic spatial gradients across the array and that random variations account for 99% of total variability.
ISSN:0894-6507
1558-2345
DOI:10.1109/TSM.2015.2439275