Passivation of surface defects on InGaAs (001) and (110) surfaces in preparation for subsequent gate oxide ALD

• Main Authors: Edmonds, M., Kent, T. J., Chang, M., Kachian, J., Droopad, R., Chagarov, E., Kummel, A. C.
• Format: Conference Proceeding
• Language: English
• Subjects: Annealing; Hydrogen; Rough surfaces; Surface cleaning; Surface roughness
• ISSN: 1524-766X; 2690-8174
• DOI: 10.1109/VLSI-TSA.2015.7117580

In 0.53 Ga 0.47 As contains an intrinsically high electron mobility making it an attractive alternative semiconductor material for use in the channel region of MOSFET devices. The semiconductor/oxide interface can degrade device performance through interfacial roughness or formation of surface defects containing electronic trap states that act to pin the surface Fermi level. Tri-gate structured field effect transistors (finFETs) are currently being implemented into commercialized logic chips, making defect reduction and passivation of the semiconductor planar and sidewall crystallographic faces critical in order to create an ideal interface between the semiconductor and the gate oxide. For InGaAs(001) based finFETs to become potential for commercial implementation, in-situ III-V surface cleaning or defect passivation techniques must be compatible with both the InGaAs (001) and (110) surfaces. STM was employed to show air exposed InGaAs (001) and (110) samples can be restored to the cleanliness of MBE grown samples through atomic hydrogen dosing and thermal annealing. STM was also employed to characterize the in-situ self-limiting CVD of a silicon hydride control layer used to passivate the missing dimer defect unit cells of the arsenic rich InGaAs(001)-(2×4) surface. Surface defect densities are compared and quantified throughout several STM images following the surface cleaning and passivation techniques.