Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS ima...

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Bibliographic Details
Main Authors: Hsiang-Hung Chang, Zhi-Cheng Hsiao, Jen-Chun Wang, Chun-Hsien Chien, Cheng-Ta Ko, Chau-Jie Zhan, Yu-Wei Huang, Yu-Chen Hsin, Chung-Chih Wang, Pei-Jer Tzeng, Cha-Hsin Lin, Chia-Hsin Lee, Ting-Sheng Chen, Wei-Chung Lo, Tzu-Kun Ku, Yung-Fa Chou, Ding-Ming Kwai, Ming-Jer Kao
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Bonding
CMOS image sensors
Dry etching
Stacking
Three-dimensional displays
Online Access:Request full text
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Summary:A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.
ISSN:1524-766X
2690-8174
DOI:10.1109/VLSI-TSA.2015.7117587