Multiplexing Sense-Amplifier-Based Magnetic Flip-Flop in a 28-nm FDSOI Technology

• Published in: IEEE transactions on nanotechnology 2015-07, Vol.14 (4), p.761-767
• Main Authors: Cai, Hao, Wang, You, Zhao, Weisheng, de Barros Naviner, Lirida Alves
• Format: Article
• Language: English
• Subjects: Clocks; Integrated circuit reliability; Latches; Logic gates; Magnetic tunneling; Transistors
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2015.2438017

A novel low-power nonvolatile magnetic flip-flop is introduced in this paper. The perpendicular magnetic anisotropy spin torque transfer magnetic tunnel junction (STT-MTJ) is used to design the hybrid MTJ/CMOS circuit, which is implemented with 28-nm high-κ metal gate and planar ultrathin body and buried oxide fully depleted silicon on insulator technology. The proposed flip-flop structure named SA-MFF shares a sensing amplifier for normal flip-flop mode and nonvolatile data sensing mode. The modified latch at output stage improves flip-flop latency. The proposed SA-MFF is symmetrical, which provides an equal delay for both true and complementary outputs. It can strengthen weak input signals (minimum 300 mV) and latch them to supply voltage. Forward body biasing transistors allow for fast operation and minimum energy consumption across all modes. The proposed SA-MFF achieves 45.2-ps latency, 50.1-ps clock to output delay, 12.71 μW active power and 343.6 nW of leakage power with 1-V supply voltage, and 6.47-μm × 4.54 μm layout area. Moreover, reliability issues are highlighted with reliability-aware simulations. Process variations of transistors/MTJs and stochastic characteristics of MTJs are investigated. Clock jitter effect and flip-flop metastability are studied.