A 40-Gb/s 310-fJ/b Inverter-Based CMOS Optical Receiver Front-End

This letter presents a low-power, 40-Gb/s optical receiver front-end fabricated in a 65-nm CMOS technology. Using an inverter-based topology for both the transimpedance amplifier and the post amplifier, high energy efficiency has been obtained. Cascaded amplifiers with transconductance and transimpe...

Full description

Saved in:
Bibliographic Details
Published in:IEEE photonics technology letters 2015-09, Vol.27 (18), p.1931-1933
Main Authors: Park, Kangyeob, Oh, Won-Seok
Format: Article
Language:English
Subjects:
Bandwidth
CMOS
Integrated optics
inverter-based shunt-feedback
Optical amplifiers
Optical fibers
optical receiver
Optical receivers
post amplifier (PA)
transimpedance amplifier (TIA)
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This letter presents a low-power, 40-Gb/s optical receiver front-end fabricated in a 65-nm CMOS technology. Using an inverter-based topology for both the transimpedance amplifier and the post amplifier, high energy efficiency has been obtained. Cascaded amplifiers with transconductance and transimpedance combinations are utilized to acquire a bandwidth of 29.6 GHz. A low-dropout voltage regulator is applied to reduce the supply noise of the single-ended amplifiers. The prototype chip excluding output buffer consumes only 12.4 mW (310 fJ/b) at a 1.2 V single supply, and the integrated input referred noise is 9.2 μA rms .
ISSN:1041-1135
1941-0174
DOI:10.1109/LPT.2015.2447283