Multi-level Shared Caching Techniques For Scalability In VMP-MC

The problem of building a scalable shared memory multiprocessor can be reduced to that of building a scalable memory hierarchy, assuming interprocessor communication is handled by the memory system. In this paper, we describe the VMP-MC design, a distributed parallel multi-computer based on the VMP...

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Bibliographic Details
Main Authors: Cheriton, D.R., Goosen, H.A., Boyle, P.D.
Format: Conference Proceeding
Language:English
Subjects:
Buildings
Computer science
Contracts
Hardware
Memory management
Optical fibers
Permission
Scalability
Semiconductor device measurement
Supercomputers
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Summary:The problem of building a scalable shared memory multiprocessor can be reduced to that of building a scalable memory hierarchy, assuming interprocessor communication is handled by the memory system. In this paper, we describe the VMP-MC design, a distributed parallel multi-computer based on the VMP multiprocessor design, that is intended to provide a set of building blocks for configuring machines from one to several thousand processors. VMP-MC uses a memory hierarchy based on shared caches, ranging from on- chip caches to board-level caches connected by busses to, at the bottom, a high-speed fiber optic ring. In addition to describing the building block components of this architecture, we identify the key performance issues associated with the design and provide performance evaluation of these issues using trace-drive simulation and measurements from the VMP. This work was sponsored in part by the Defense Advanced Re- search Projects Agency under Contract N00014-88-K-0619.
ISSN:1063-6897
2575-713X
DOI:10.1109/ISCA.1989.714520