Systematic Hardware Adaptation Of Systolic Algorithms

In this paper we propose a methodology to adapt Systolic Algorithms to the hardware selected for their implementation. Systolic Algorithms obtained can be efficiently implemented using Pipelined Functional Units. The methodology is based on two transformation rules. These rules are applied to an ini...

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Bibliographic Details
Main Authors: Valero-Garcia, M., Navarro, J.J., Llaberia, J.M., Valero, M.
Format: Conference Proceeding
Language:English
Subjects:
Concurrent computing
Data flow computing
Design methodology
Flow graphs
Hardware
Matrix decomposition
Parallel programming
Permission
Synthetic aperture sonar
Systolic arrays
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Summary:In this paper we propose a methodology to adapt Systolic Algorithms to the hardware selected for their implementation. Systolic Algorithms obtained can be efficiently implemented using Pipelined Functional Units. The methodology is based on two transformation rules. These rules are applied to an initial Systolic Algorithm, possibly obtained through one of the design methodologies proposed by other autors. Parameters for these transformations are obtained from the specification of the hardware to be used. The methodology has been particularized in the case of one-dimensional Systolic Algorithms with data contraflow.
ISSN:1063-6897
2575-713X
DOI:10.1109/ISCA.1989.714543